Introduction

The NIOS is a proprietary softcore processor from Altera. It is based on a 32-bit RISC core. The NIOS processor is programmed using Quartus with the Qsys interface.

It features the Avalon bus. The NIOS processor has several possible versions: NIOS II Fast, NIOS II/e Standard, and NIOS II/E Economy. These different versions allow for various optimizations of the processor, enabling you to choose the NIOS II version that best fits your needs. Let’s take a closer look at the differences between these versions.

Avalon Bus

The Avalon interface allows connecting an arbitrary number of master and slave elements, ensuring good data exchanges between them, as long as they comply with the interface specifications.

It serves as the interface between the components of the NIOS II processor. There are six possible interfaces:

  • Avalon-MM: A connection that allows read/write operations based on addresses in a master/slave mode for internal FPGA elements.

  • Avalon-MM Tristate: A connection that allows read/write operations based on addresses in a master/slave mode for external elements sharing the bus.

  • Avalon-ST: A connection that enables unidirectional data transfers, potentially multiplexed.

  • Avalon-Clock: A connection that allows sending or receiving clock and reset signals to synchronize system elements.

  • Avalon-Interrupt: A connection that allows components to signal events.

  • Avalon-Conduit: A connection that provides direct access to the internal components of a Qsys system.

A) Avalon-MM

The Avalon-MM connection enables exchanges between one or more masters and one or more slaves through a specific interconnection system.

There are three types of Avalon-MM connections:

  • Avalon MM Slave

  • Avalon MM Master

  • Avalon MM Tristate Slave

For the Avalon MM Master interface, there are two types of transfers:

  • Classic Read/Write: Wait for the master to be ready to read only part of a word from memory.

  • Write Burst and Read Burst: Perform burst reads and writes. Additional signals specify how many memory locations will be retrieved. Unlike classic read/write, which reads the entire memory, burst operations fetch a chunk of memory at once.

Address Decoding

There is no address decoding within the NIOS processor components. A chip select is generated by the component. The address decoder is automatically generated to respect the memory map, so there is no need to recompile your program if you modify it.

Multiplexing the Data Path

The data path is multiplexed to create a write path from the active master to the slaves, and a read path from the slaves back to the master.

Insertion of Wait States

Wait states extend the duration of a transfer by one or more clock cycles. This is useful for managing slaves with long response times, informing the master to wait until the slave is ready.

Pipelined Reading

It’s possible to pipeline a transfer from a master to a slave to improve data flow between them.

Data Size Management

There are two modes for address management:

  • Dynamic Bus Size: Allows a master to access any slave memory.

  • Address Alignment: A word from the slave corresponds exactly to a word from the master. Only one transfer is performed. This method affects the slave’s words to the lower bits of the master and fills with zeros. It works only if the master has a larger width than the slave.

Master Arbitration in Multi-Master Systems

Each master has a share of a given slave. The arbiter allocates transfers to each master in proportion to their share, then moves to the next. A slave port can have a minimum number of shares representing the minimum number of transfers with that component.

Managing Multiple Clocks

Multiple ports can operate with different clocks. Each port is tied to a single clock.

  • The Master imposes the address, clock, and data.

  • Handshake captures control signals and places the master in wait.

  • A transfer request is made by the slave’s handshake.

  • Synchronization occurs with the slave clock.

  • When the slave transfer is complete, an acknowledgment is sent to the master’s handshake.

  • Synchronization occurs with the master clock.

  • The master handshake removes the wait condition.

Five clock cycles are needed in each domain for each transfer.

Metastability

This occurs when the clock edge arrives when data reaches the master, and the master and slave do not share the same clock. To avoid this, data is transmitted first to the master’s clock rhythm and then to the slave’s.

Interrupt Management

If the slave ports generate interrupt requests, interrupt controllers are inserted for each master port that accepts interrupts. Two types of controllers are possible: Soft priority and Hard priority. This allows selecting the most important interrupt and handling it with priority.

B) Avalon-ST

Avalon-ST is a unidirectional high-bandwidth, low-latency connection (packet transmission, potentially interleaved).

  • Streaming Interface: A unidirectional connection between a transmitter and a receiver, which must acquire data on the next clock cycle. It manages packets, images, and other data.

There are different types of transfers:

  • Transfer without Backpressure

  • Packet Transfers

  • Transfer with Backpressure

Accelerating Processing: A sequence of instructions.

C) Different Types of Instructions

  • Combinational Instruction: A logic block capable of performing its operation in one clock cycle.

  • Multi-cycle Instruction: A logic block that requires multiple clock cycles to perform its operation.

  • Extended Instruction: A logic block capable of executing several instructions on inputs dataa and datab.

  • Internal Register Instruction: A logic block capable of executing several instructions using the processor’s registers.

 

Quartus Qsys

 

Now, let’s see the Avalon bus in action with Quartus. First, you need to open the Qsys part of Quartus. To do this, you must have opened or created a new project in Quartus. If you don’t know how to create a project or install the software, you can refer to our dedicated guide for that.

Once the project is open, click on Tools in the toolbar, then select Platform Designer.

Here’s the page that opens:

You click on “New Component” to view all available components::

On this first page, you give the name that your component will have, here it is composant_cours:

 

In the Files section, we will load a VHDL or Verilog file that describes the behavior of our component. The file must be part of the project we previously created. Here, we’ve loaded the tp_A2 file, which will describe the behavior of our component:

Now, let’s see how to create an interface and signals for our component. If you encounter errors, especially with the clock, make sure that the VHDL file you provided is not empty and actually contains the behavior of your component. Otherwise, you will run into some errors when generating the interface.